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POST : ASIC RTL Design Lead
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LOCATION : Noida
TECH STACK :ASIC RTL Verilog CDC Lint
REQ EXPERIENCE :7 years
JD :
Strong ASIC RTL design (Verilog/SystemVerilog), CDC, Lint Experience in micro-architecture, integration, and debugging Exposure to synthesis, timing, and low-power design Team leadership and cross-functional collaboration skills
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